Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after\r\npartitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical\r\nconnections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system\r\nfrequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set\r\nof constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an\r\niterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the\r\nintra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem.Many scenarios\r\nare proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system\r\nfrequency is improved by an average of 12.8% compared to constructive routing algorithm.
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